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Consider a memory system with a level 1 cache of 32KB and DRAM of 512MB with the processor operating at 1GHz. The latency to L1 cache is one cycle...

Consider a memory system with a level 1 cache of 32KB and DRAM of
512MB with the processor operating at 1GHz. The latency to L1 cache is one cycle
and the latency to DRAM is 100 cycles. In each memory cycle, the processor fetches
four words (cache line size is four words). What is the peak achievable performance
of a dot product of two vectors? Note: where necessary, assume an optimal cache
placement policy.

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