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 Given a main memory DRAM where each chip contains 4 banks and each

bank has a 4 byte Row Buffer (and there are four chips per rank for our 32-bit machine).  Using the DRAM command timing given in slide 5A.20 what is the number of memory cycles needed to read in an 8 word block of data from consecutive word addresses (e.g., word0, word1, word2, word3, word 4, word5, word6, word7) if bank addressing is not interleaved?  What is the number of memory cycles needed if bank addressing is interleaved as on slide 5A.37
slide 5A.20 :
opening to bank if closed
10 units if same bank
2 units if different bank same chip
copying the requested row's bank data to its bank's row buffer 1 unit
issuing read and or write which reads/writes from/to the row buffer 1 unit
closing the bank by writing from the row buffer back to the dram 1 unit
Slide 5A.37:
bank 0
0   1   2   3  
16 17 18 19
bank 1 ......

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Given a main memory DRAM where each chip contains 4 banks and each bank has a 4 byte Row Buffer (and there are four chips per rank for our 32-bit
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