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EE 2301 Introduction to Digital Systems Design UMN Fall 2016 Homeworks # 4 and 5 Due Tue., Nov. 15, 2016, at 9:45am in class 1. Designing a...

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EE 2301 UMN Introduction to Digital Systems Design Fall 2016 Homeworks # 4 and 5 Due Tue., Nov. 15, 2016, at 9:45am in class 1. Designing a Sequential Circuit The Collatz conjecture is a famous open problem in mathematics, proposed by Lothar Collatz in 1937. Consider the following iterative procedure. For any positive integer x , if x = 1 stop; else if x is odd, let x = 3 x + 1; else let x = x/ 2. The conjecture is that, starting with any positive integer x , the procedure always terminates with x = 1. For instance, starting with x = 5, one follows the sequence 16, 8, 4, 2 and 1. Proving this is evidently difficult. Paul Erd¨ os said about the conjecture: “Math- ematics is not yet ready for such problems”. He offered a monetary reward of $500 for its solution. You are not asked to prove the Collatz conjecture on this homework. Rather you are asked to design a digital circuit to implement the procedure, on 8-bit numbers. Since one can only represent integers from 0 to 255 with 8 bits, the procedure either terminates with x = 1 or else terminates with an overflow when 3 x + 1 > 255. For instance, starting from x = 27, one follows the sequence 82, 41, 124, 62, 31, 94, 47, 142, 71, 214 and 107. And this point, 3 x + 1 = 322, so there is an overflow.
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EE 2301, Fall ’16 2 (a) Design a combinational circuit to implement a single step of the Collatz procedure, as follows. Let the bits X = ( X 0 ,...,X 7 ) represent the initial value of x , least significant bit first. Let the bits Y = ( Y 0 ,...,Y 7 ) represent the result. Let end be a bit that indicates that x = 1; let over be a bit that indicates that there is an overflow. Design your circuit with inputs X and outputs Y , end and over , as shown in Figure 1, such that if X = 1, then end = 1 and over = 0; else if there is an overflow, then end = 0 and over = 1; else if X is odd, then Y = 3 X + 1 and end = over = 0; else Y = X/ 2 and end = over = 0. In your design, you may use standard modules such as adders, comparators and multipliers. However, you should specify how each of these modules is built from logic gates. In addition to drawing gate schematics, you are encouraged to provide your answer in the form of textual hardware description. (This is not required.) You can use Verilog, VHDL, or even a general-purpose language such as C, Java, or Python. Or you use a generic form such as this: FullAdd(a, b, ci: s, co) { g0 = XOR(a, b); g1 = AND(a, b); g2 = AND(ci, g0); s = XOR(ci, g0); co = OR(g1, g2); } Provide an explanation of the flow of your design to assist the grader.
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