Module 5A2 Laboratory: Flip-Flops Objectives The objectives of this experiment are to: Examine the operation of the RS latch. Examine the operation...
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Module 5A2 Laboratory: Flip-Flops
Objectives
The objectives of this experiment are to:
1. Examine the operation of the RS latch.
2. Examine the operation of the D-type flip flop.
3. Examine the operation of the JK flip flop.
Introduction
A flip flop is an essential building block of many important and useful circuits, such as counters.
shift registers, and memories. Basically, a flip flop stores a zero or a one. One or more inputs are
provided to change the state of the flip flop. In this experiment we will examine the operation of
several common flip flops.
Procedure
1. Load the circuit EGA-1.MS7, shown in Figure 6A.1.
vee
4. ThCha
Key . T
HAND
Figure 6A.1: RS latch
Attach logic indicators and simulate the circuit. Which indicator is on?
2. Press 'T' several times. What happens at the Q and Q' outputs?
3. In the real world, the SPDT switch suffers from mechanical contact bounce, which in turn
generates hundreds or even thousands of edges before settling. The RS latch debounces the
switch, providing one clean edge on its output for each toggling of the input. This edge can be
used to provide a single clock pulse to a flip flop, counter, or shift register. MultiSim contains
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Module 3: Laboratory 2A: Flip-Flops
Module 3: Laboratory 2A: Flip-Flops
several built-in RS latches in the Miscellaneous Digital parts bin. Figure 6A.2 shows one
6. Load the circuit E6A-3.MS7, shown in Figure 6A.4. The D flip flop has its Q' output wired
example.
back to the D input. This enables a special mode called toggle, where the state of the output
alternates between zero and one every two clock cycles. Verify this by pressing 'T' ten times.
How many times does the logic indicator flash?
SET
VCC
BEBET
ER_LATCH
21koha
Figure 6A.2: Built-in RS latch
vec
Add the SPDT switch to the inputs with the proper pull ups and verify that the built-in RS latch
SV
works the same as the circuit in Figure 6A.1.
. IPR
ID
10 4
4. Load the circuit E6A-2.MS7, shown in Figure 6A.3, which uses the RS latch as the clock-
pulse circuit for a D-type flip flop. The data input to the flip flop is controlled by the D switch.
4. Thoha
Jop 1CLK - 10
-1CLA
74741
Key . T
HAND
vec
Key . D
-LPR
Figure 6A.4: D flip flop wired for toggle mode
ID
10 5
7. Load the circuit EGA-4.MS7, shown in Figure 6A.5.
4. Thoha
3p 1CLK -10
MANDE
-1CLR
74748
Key . T
. Thoha
HAND Z
Figure 6A.3: Type-D flip flop
5. Determine what edge the D flip flop responds to (positive or negative).
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Module 3: Laboratory 2A: Flip-Flops
Module 3: Laboratory 2A: Flip-Flops
VCC
VCC
SV
Key . P
1 0ha
Y. EV
-1PR
10 5
3p 1CLK - 10
-ICLR
ID
10
74741
Jop 1CLK - 10 6
-1CLR
74740
Key . C
Figure 6A.6: D flip flop with asynchronous inputs
Figure 6A.5: Divide-by-two circuit
10. Load the circuit E6A-6.MS7, shown in Figure 6A.7.
Verify (using the oscilloscope or logic analyzer) that the frequency of the waveform at the Q
VCC
SV
output is 500 Hz.
Key . P
8. Add a second D flip flop (wired for toggle). The Q output of the first flip flop connects to the
18 0ha
clock input of the second. What is the frequency at the second Q output?
Y . EV
9. Load the circuit EGA-5.MS7, shown in Figure 6A.6. Now the asynchronous preset and clear
- 1PR
inputs are used. The upper input (connected to the P switch) is the Preset input, which causes Q
MM
13
10 14.
to go high, regardless of the clock state, whenever Preset is low. The lower input is the active-
1koha
Jop ACLK
low Clear input, which forces Q low when active. Verify the operation of the Preset and Clear
-10 14
inputs by toggling &quot;P' and 'C' during simulation.
-ICLR
7476N
vec
SV
Key . C
Figure 6A.7: JK flip flop wired for toggle mode
11. With the J and K inputs tied high, the output of the JK flip flop will toggle to the opposite
state upon each negative edge of the clock. Verify that the JK flip flop is negative-edge triggered.
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Module 3: Laboratory 2A: Flip-Flops
12. Verify that the Preset and Clear inputs are active low (using 'P' and 'C').
13. The truth table for the JK flip flop is shown in Table 6A.1. Verify the four modes of
operation.
K
Q
0
N/C
N/C
0
1
0
Table 6A.1: Truth table for the JK flip flop
When J and K are both low, the outputs do not change state when the flip flop is clocked. When J
is low and K is high, Q goes low after the next clock pulse. This mode is called clear. When J is
high and K is low, Q is set after the next clock pulse. Toggle mode is selected when J and K are
both high.
Discussion
While reviewing your data and results, provide detailed answers to each of the following:
1. How does the built-in RS latch in the Miscellaneous Digital parts bin differ from the
NAND gate circuit in EGA-1.MS7?
2. Do the type-D and JK flip flops respond to the same clock edge?
3. Explain how toggle mode is the same as division by two.
4. What is the difference between a synchronous input (D. J, or K) and an asynchronous
input (PR or CLR)?
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