Design a Mealy finite state machine with input X and output Z. The output Z should be asserted
for one clock cycle whenever the sequence ...0111 or ...1000 has been input on X. The patterns may overlap. For example, X= ..0000111000...should generate the output stream Z= ...0000001001...
a) Complete the state diagram for the sequencer detector without concern for state minimization.
b) Complete the state table for the state diagram derived in part a).
c) Minimize the state table using the implication chart.
d) Assign states using a direct mapping of bits with the order of state in the tables, for example S0 = 000, S1= 001... S5=101..
e) Implement the encoded, reduced state table with D flip-flops. Show the minimized logic equations for the next and outputs.
f) Repeat e) using J-K flip flops.
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