Implement the finite state machine for the cipher lock using the Atmel ATF750CL CPLD.
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Implement the finite state machine for the cipher lock using the Atmel ATF750CL CPLD. Your finite state machine should implement the state transition diagram you developed in Problem Set 6 with your particular access code. If you needed to make corrections to the state machine for Project 2 versus your Problem Set 6 solution, you will also need to use those corrections for this project.

Allow the user to generate the input signals B3 - B0 using the tactile switches in your lab kit. Use a fifth tactile switch for generating the input R (Reset), that asynchronously resets the system to state S0. Use a 27 kΩ resistor as a pull up resistor between one terminal of switch and the input to the CPLD logic. Indicate the output signals L and A, B, and C with LEDs. Use a 330 Ω resistor in series with each LED to limit current. Your implementation should conform with the circuit diagram shown in Figure 2. In addition to the wiring shown, your flip-flop outputs need to be assigned to pins on the CPLD; use your discretion in selecting these assignments.

  1. Unfortunately, the Atmel ATF750CL CPLD power consumption is fairly high. Sometimes, the myDAQ cannot source sufficient current to operate the CPLD. You may need to use the power supplies available in 302 EE West, or another 5V supply capable of supplying at least 200 mA.
  2. As in project 1, generate a 0.2 Hz clock circuit using the CD4541B programmable timer. Use the yellow LED to display the state of the clock signal. The yellow LED should be lit when the logical state of the clock signal is high.
  3. Connect the input switches and output LEDs as indicated in Figure 2. Note that pressing a given button represents the logic high state, however, the corresponding logic level signal at the CPLD peripheral pin is at logic low state. For example, when the user presses the button L the value of L is logic high while the corresponding logic level signal at pin 2 is low. Your code for the CPLD should expect this behavior. Also, bear in mind that both the CPLD and the timer IC should both have bypass capacitors; these are not shown in the schematic.
  4. Implement the finite state machine using the CUPL state machine syntax and adhere to the following guidelines. • Use meaningful header information. Your name should appear as the designer. Also, provide suitable
  5. project and company names, and specify the correct device.
  6. • Comment you code. Clearly define the input and output pin assignments. As an example, review the WinCUPL code in Laboratory #21.
  7. Measure the maximum current drawn by your circuit using the myDAQ as this information is need for a future problem assignment.

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Screen Shot 2019-12-11 at 3.10.35 PM.png

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