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(2 points) Show how the value ASCII "MIRIAM" is stored as hexadecimal in memory in Little Endian format starting at location 100 hexadecimal.

2. (2 points) Show how the value ASCII “MIRIAM” is stored as hexadecimal in memory in Little Endian format starting at location 100 hexadecimal. Assume that each memory location stores two ASCII characters.

Memory Location Value Stored

3. (2 points) Draw the block diagram for the hardware that implements the following:

y + xz: AR  BR + CR

where AR, BR and CR are n-bit registers and x, y, and z are control variables. Include the logic gates for the control function and a block labeled ‘adder’ for the addition function. (Remember that that the symbol + designates an OR operation in the control function, but an arithmetic plus in a microoperation.)

4. (8 points) Perform the computations below given the two 8-bit binary words:
A = 1100 1010
B = 1001 0110

Compute Answer
(A v B)’
(A ^ B)

5. (12 points) The content of AC in the basic computer is hexadecimal 79A0 and the initial value of E is 1. Determine the contents of AC, E, PC, AR, and IR in hexadecimal in each of the register –reference instructions from CLA to HLT. The initial value of PC is hexadecimal 156.

Initial 1 79A0 156 - -

6. (8 points) An instruction at address 106 in the basic computer has I = 0, and an address part equal to 417 (all numbers are hexadecimal). The memory word at address 417 contains 16AB and the content of AC is 5E34. Go over the instruction cycle and determine the contents of registers PC, AR, DR, AC, and IR for each of the seven memory-reference instructions.

Initial 106 - - 5E34 -

7. (10 ¬¬¬¬¬¬points) The following program is a list of instructions for the Basic Computer in hexadecimal code. The computer executes the instructions starting from address 100.
What are the contents of AC and the memory at address 104 when the computer halts? Show the instructions in the sequence that they are executed.

See Mano’s problem 6-2 and the answer in the Module 3 conference in Note 5.

Location Instruction
100 2107
101 7200
102 5104
103 7001
104 0000
105 7020
106 C104
107 AA55

Location Instruction comment AC
100 2107

The accumulator (AC) has the value ____;
memory location 104 has the value ____

8. (12 points) For X = 1110 0011 1001 0100, show the result of the following independent operations (i.e. each instruction occurs with X starting at the value above):

a) Shift-right ____ ____ ____ ____

b) Shift-left ____ ____ ____ ____

c) Circular Shift-left ____ ____ ____ ____

d) Circular Shift-right ____ ____ ____ ____

e) Arithmetic Shift-left ____ ____ ____ ____

f) Arithmetic Shift-right ____ ____ ____ ____
9. (16 points) Write code that performs the computation:
X = A + B + C * D +* E / F
using CPUs that have the following instruction formats: Do not modify the values of A, B, C, D, E, or F. If necessary, use a temporary location T to store the intermediate results.
a. three-operand instructions

b. two-operand instructions

c. one-operand instructions

d. stack instructions

10. (16 points) A two-word instruction is stored at location 200 with its address field at location 201 (all numbers in hexadecimal). The first word of the instruction specifies the operation code and mode; the second word specifies the address part.
The values of the program counter (PC register), a general register (R1), the index register (XR), the base register (BR), and certain addresses in memory are as shown below.
Evaluate the effective address and the value that is loaded into the AC if the addressing mode of the instruction is:

Addressing Mode Effective address Value of the operand loaded into the AC
a) Immediate
b) Direct addressing
c) Indirect addressing
d) Register
e) Register indirect
f) Relative address
g) Base register addressing
h) Indexed addressing

Registers Address Content
PC =98 200 Load to AC; Mode
201 Address = 600
R1 = 900 202 Next instruction
: :
XR = 300 300 600
: :
BR = 200 400 300
: :
AC = ? 500 700
: :
600 800
: :
700 500
: :
800 950
: :
900 850

11. (10 points) For the ALU of figure 8-2 with tables 8-1 and 8-2.

a) Specify the 14-bit control word that must be applied to implement the following microoperation:

R2 R4 – R6

SELA (3 bits) SELB
(3 bits) SELD
(3 bits) OPR (5bits) Control Word

b) Determine the microoperation that will be executed in the processor when the following 14-bit control word is applied:

(3 bits) SELB
(3 bits) SELD
(3 bits) OPR (5bits) Microoperation

12. (6 points) Given the following set of events, show which routines the CPU is executing for times 0 to 100 ns. Each handler routine (with its interrupt request) takes 20 ns to complete. The priority of the interrupts ranges from IRQ6 as the highest priority interrupt to IRQ0 as the lowest priority interrupt.

Time Action
0 ns Start of main program
10 ns IRQ1
20 ns IRQ3
35 ns IRQ4
50 ns IRQ6
Time Action

0 ns: Start of Main Program
10 ns: IRQ1

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