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I need to have the following homework answer: Show how the value ASCII "MIRIAM" is stored as hexadecimal in memory in Little Endian format starting...

I need to have the following homework answer:

1. Show how the value ASCII “MIRIAM” is stored as hexadecimal in memory in Little Endian format starting at location 100 hexadecimal. Assume that each memory location stores two ASCII characters.

Memory Location Value Stored
100
101
102




2. Perform the computations below given the two 8-bit binary words:
A = 1100 1010
B = 1001 0110

Compute Answer
(A v B)’
(A NOR B)
(A ^ B)
(A AND B)


3. The content of AC in the basic computer is hexadecimal 79A0 and the initial value of E is 1. Determine the contents of AC, E, PC, AR, and IR in hexadecimal in each of the register –reference instructions from CLA to HLT. The initial value of PC is hexadecimal 156. Fill in the AC, PC, AR and IR

E AC PC AR IR
Initial 1 79A0 156 - -
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT






4. An instruction at address 106 in the basic computer has I = 0, and an address part equal to 417 (all numbers are hexadecimal). The memory word at address 417 contains 16AB and the content of AC is 5E34. Go over the instruction cycle and determine the contents of registers PC, AR, DR, AC, and IR for each of the seven memory-reference instructions.

PC AR DR AC IR
Initial 106 - - 5E34 -
AND
ADD
LDA
STA
BUN
BSA
ISZ




5. For X = 1110 0011 1001 0100, show the result of the following independent operations (i.e. each instruction occurs with X starting at the value above):

a) Shift-right ____ ____ ____ ____

b) Shift-left ____ ____ ____ ____

c) Circular Shift-left ____ ____ ____ ____

d) Circular Shift-right ____ ____ ____ ____

e) Arithmetic Shift-left ____ ____ ____ ____

f) Arithmetic Shift-right ____ ____ ____ ____


6. Write code that performs the computation:
X = A + B + C * D +* E / F
using CPUs that have the following instruction formats: Do not modify the values of A, B, C, D, E, or F. If necessary, use a temporary location T to store the intermediate results.

a. three-operand instructions
b. two-operand instructions
c. one-operand instructions
d. stack instructions


7. Given the following set of events, show which routines the CPU is executing for times 0 to 100 ns. Each handler routine (with its interrupt request) takes 20 ns to complete. The priority of the interrupts ranges from IRQ6 as the highest priority interrupt to IRQ0 as the lowest priority interrupt.

Time Action
0 ns Start of main program
10 ns IRQ1
20 ns IRQ3
35 ns IRQ4
50 ns IRQ6
Time Action

0 ns: Start of Main Program
10 ns: IRQ1

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