NMOS: VTHN=0.25V, n=350cm2
/(Vs), Cox=0.95 F/cm2
PMOS: VTHP=-0.25V, p=175cm2
/(Vs), Cox=0.65 F/cm2
a) In an inverter, the width of the NMOS is 1um. Using Velocity Saturated model to
make Idsatp=Idsatn, what’s the width of the PMOS? (L=100nm in this problem)
c) In a NAND2 gate, keep the PMOS the same width as you got in part (a), if you still
want to make Idp=Idn, what’s the width of the stacked NMOS?
e) Repeat part (c) for a NAND3 gate.
Recently Asked Questions
- Write the negation of the statement: " Every function is not differentiable at x=c or it is continuous at x=c "
- For the reaction shown here 2NH 3 (g) reaction 3H 2 (g) + N 2 (g) The equilibrium constants were found to be [NH 3 ] = 0.250 M [H 2 ] = 0.650 M [N 2 ] =0.800 M
- Where should companies spend most of their quality funds: on prevention, inspection, internal failure or external failure costs? Detail and reasoning please.