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Problem 1 Velocity Saturated Model NMOS: VTHN=0.25V, n=350cm2 /(Vs), Cox=0.95 F/cm2 , vsat=107 cm/s, =0 PMOS: VTHP=-0.25V, p=175cm2 /(Vs), Cox=0.

Problem 1 Velocity Saturated Model
NMOS: VTHN=0.25V, n=350cm2
/(Vs), Cox=0.95 F/cm2
, vsat=107
cm/s, λ=0
PMOS: VTHP=-0.25V, p=175cm2
/(Vs), Cox=0.65 F/cm2
, vsat=107
cm/s, λ=0
a) In an inverter, the width of the NMOS is 1um. Using Velocity Saturated model to
make Idsatp=Idsatn, what’s the width of the PMOS? (L=100nm in this problem)

c) In a NAND2 gate, keep the PMOS the same width as you got in part (a), if you still
want to make Idp=Idn, what’s the width of the stacked NMOS?

e) Repeat part (c) for a NAND3 gate.

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