Write a testbench stimulus for the below 8-bit Shift-Left Register with Positive-Edge Clock, Serial In and Serial Out. Start with all ones after the 8th=bit shifted to the left all zeros.
module left_shifter(SHIFTEN, DIN, DOUT);
reg [7:0] tmp;
always @(posedge SHIFTEN)
tmp <= tmp << 1;
tmp <= DIN;
assign DOUT = tmp;
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