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HARDWARE IMPLEMENTATION OF PAN & TOMPKINS QRS DETECTION ALGORITHM1 Christos Pavlatos*, Alexandros Dimopoulos*, G. Manis** and G....

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HARDWARE IMPLEMENTATION OF PAN & TOMPKINS QRS DETECTION ALGORITHM 1 Christos Pavlatos*, Alexandros Dimopoulos*, G. Manis** and G. Papakonstantinou* * National Technical University of Athens Dept. of Electrical and Computer Engineering Zografou 15773, Athens Greece ** University of Ioannina Dept. of Computer Science P.O. Box 1186, Ioannina 45110 Greece {pavlatos, alexdem, papakon}, [email protected] Abstract 1 : This paper presents a hardware implementation of the Pan and Tompkins QRS detection algorithm, described in Verilog HDL (Hardware Design Language). The generated source has been simulated for validation, synthesized and tested on a Xilinx FPGA (Field Programmable Gate Array) board using the European ST-T database. To the best of the authors’ knowledge this is the first attempt for the hardware implementation of the Pan and Tompkins QRS detection algorithm, in reconfigurable FPGA boards. The generated hardware achieves a speed up of 250% compared to the software implementation. Given that and the vital importance of a fast and accurate QRS detection, the hardware implementation seems a promising approach. Introduction The QRS detection algorithm introduced by Pan and Tompkins [1] is the most widely used and often cited algorithm for the extraction of QRS complexes from electrocardiograms. The methodology followed is that the ECG is passed through a low-pass and a high-pass filter in order to remove noise from the signal. Then the filtered signal is passed through derivative, squaring and window integration phases. Finally, a thresholding technique is applied and the R-peaks are detected. This work presents the hardware implementation of the Pan-Tompkins algorithm. The Verilog [2] hardware description language has been used. The building blocks and the actual implementation were designed, tested and evaluated using the ISE tool available from Xilinx [3]. The comparison of our hardware implementation with an equivalent software approach showed that the necessary clock cycles are significantly less for the hardware implementation. 1 This work is co - funded by the European Social Fund and particularly the Program “Pened 2003”. The rest of the paper is structured as follows. The following section outlines some interesting QRS detection algorithms and describes in more detail the one proposed by Pan and Tompkins. The next chapter presents the general architecture of the proposed system, while implementation details are given in the next two chapters. The final section summarizes this work. QRS Detection Algorithms Several QRS detection algorithms have been proposed in the literature [22], [23]. Algorithms [4], [5] and [6] are based on the amplitude and the first derivative. In [4] a point is classified as QRS candidate when three consecutive points of the first derivative exceed a positive threshold (ascending slope) followed within the next 100ms by two consecutive points which exceed a negative threshold (descending slope). Fraden and Neuman [5] developed a QRS detection scheme where a threshold is calculated as a fraction of the peak value of the ECG. Gustafson [6] suggested that a point is a QRS peak candidate when the first derivative and the three next derivative values exceeds a threshold and the next two sample points have positive slope amplitude products. Algorithms [7] and [8] are based on the first derivative only. In [7] the first derivative is calculated by a given formula and the slope threshold is calculated as a fraction of the maximum slope for the first derivative. In [8] the derivative and the derivative of the next three points should exceed the threshold. Algorithms [9] and [10] are based on the first and second derivatives. Balda [9] suggested searching values exceeding the threshold in a weighted summation of the first and second derivative. Ahlstrom and Tompkins in [10] proposed that the absolute values of the first derivative are smoothed and added with the absolute values of the second derivative. Two thresholds are used, a primary and secondary one. A point is candidate for QRS peak point when the primary
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threshold is exceeded and the secondary threshold is exceeded for the next six consecutive points. Algorithms [11] and [12] are based on digital filters. Apart from the above referenced papers, a more detailed description of those ([4]-[12]) algorithms can be found in [13]. QRS detection algorithms have been proposed by our research group based on the length transformation and on syntactic methods [14], [24], [25], [26], [27], [28]. These algorithms calculate the length and energy signals of the ECG and identify peaks using variations and thresholds in these signals. Relative work which proposes alternative approaches to QRS detection includes [15-20]. Pan & Tompkins QRS detection algorithm One of the most popular QRS detection algorithms, included in virtually all biomedical signal processing textbooks, is that introduced by Pan and Tompkins in [1]. An overview of the algorithm follows. Figure 1 shows a graphical representation of the basic steps of the algorithm. Figure 1: A graphical representation of the algorithm. The signal passes through filtering, derivation, squaring, and integration phases before thresholds are set and QRS complexes are detected In the first step the algorithm passes the signal through a low pass and a high pass filter in order to reduce the influence of the muscle noise, the power line interference, the baseline wander and the T-wave interference. The low-pass filter is described by the formula: ) 12 ( ) 6 ( 2 ) ( ) 2 ( ) 1 ( 2 ) ( & ± & & ± & & & ² n x n x n x n y n y n y and the high-pass one is given by: ) 32 ( 32 1 ) 17 ( ) 16 ( ) ( 32 1 ) 1 ( ) ( & ± & & & ± & & ² n x n x n x n x n y n y After filtering, the signal is differentiated to provide the QRS slope information using the following formula: 1 y( n ) [ 2x( n ) x( n 1) x( n 3) 2x( n 4 )] 8 ² ± & & & & & Then the signal is squared point by point making all data point positive and emphasizing the higher frequencies. ) ( ) ( 2 n x n y ² After squaring, the algorithm performs sliding window integration in order to obtain waveform feature information. )] ( ... )) 2 ( ( )) 1 ( ( [ 1 ) ( n x N n x N n x N n y ± ± & & ± & & ² where N is the size of the sliding window and depends on the sampling rate. For a sampling rate of 200 samples/sec the size of the window can be 30 samples. A temporal location of the QRS is marked from the rising edge of the integrated waveform. In the last step two thresholds are adjusted. The higher of the two thresholds identifies peaks of the signal. The lower threshold is used when no peak has been detected by the higher threshold in a certain time interval. In this case the algorithm has to search back in time for a lost peak. When a new peak is identified (as a local maximum – change of direction within a predefined time interval) then this peak is classified as a signal peak if it exceeds the high threshold (or the low threshold if we search back in time for a lost peak) or as a noise peak otherwise. In order to detect a QRS complex the integration waveform and the filtered signals are investigated and different values for the above thresholds are used. To be identified as a QRS complex, a peak must be recognized as a QRS in both integration and filtered waveform. The Architecture of the Implementation The architecture of the implementation is shown in figure 2 and consists of seven modules and one memory unit. The module on the left is the control unit which is responsible for the generation of the control signals and coordinates all calculations. Each one of the six modules in the middle is responsible for a different stage of the algorithm as described in the previous section. Each one of those modules read values from the memory, perform the necessary computations and store the new values back in memory. M E M O R Y Low Pass Filter High Pass Filter Derivative Squaring Integration Decision Control Unit Control Bus Data Bus Figure 2: An overview of the architecture. The control unit coordinates the rest of the modules which perform calculations and interfere with the memory unit. Even though the implementation of the algorithm in hardware seems a complicated task, a closer look at the algorithm reveals some similarities in the calculations performed by the first five stages since the filters, the differentiation and the integration units compute
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